//=============================================================================
// File name:   seg7_basys_top.v
// Author:      Cody Cziesler
//
// Description: This module is the top-level file which is used to create a bit
//              file to program the basys2 fpga. It does the following:
//
//               1) Route the correct I/O from the I/O of the FPGA to the I/O 
//                    of seg7_top.
//
//               2) Take the 25 MHz clock input and divide it down to 762.939453
//                    Hertz based on a 16-bit counting clock divider
//
//=============================================================================
`include "include.v"

module seg7_basys_top (
  input wire        clk,
  input wire        rst_n,
  input wire        set,
  input wire  [1:0] anode_in,
  input wire  [3:0] seg_in,
  output wire [6:0] seg_out,
  output wire [3:0] anode_out,
  output wire       dp
);

// The divided clock going to seg7_top
wire clk_div;

// A 16-bit register to hold the count
reg [15:0] count;

// A 16-bit up-counter
always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    count <= 1'b0;
  end else begin
    count <= count + 1'b1;
  end
end

// Assign the divided clock to count[15] to get a ~763 Hz clock
assign clk_div = count[15];
	 
seg7_top i_seg7_top (
  .clk(clk_div),
  .rst_n(rst_n),
  .set(set),
  .seg_in(seg_in),
  .anode_in(anode_in),
  .anode_out(anode_out),
  .seg_out(seg_out),
  .dp(dp)
);

endmodule
